1. Field of the Invention
The present invention relates to memory allocation, and more particularly to a system and method for placement of stored memory elements to reduce latency in computer systems.
2. Description of the Related Art
Advances in computer technology often result in increased sensitivity to particular performance characteristics. For example, with each generation in processor technology, the transit time of a signal in flight on a wire (e.g. an RC time constant) increases with respect to the switching time of a transistor. Considering that a wire serves as a communication pathway and transistors form logic gates, reductions in communication latency may have more of an impact on processor performance than those directed toward increasing pure computational capacity.
As such line or wire latency plays a major role in the speed and responsiveness of not only processors but also any circuit including high-speed memory systems.
Therefore, a need exists for reducing an average transit time (latency) of signals in flight. A further need exists for a system and method for allocating memory locations to reduce time in flight in memory storage systems.